3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme by Prof. Yangdong Deng, Prof. Wojciech P. Maly (auth.)

By Prof. Yangdong Deng, Prof. Wojciech P. Maly (auth.)

"3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme"elaborates the concept that and value of three-d (3-D) VLSI. The authors have constructed a brand new 3D IC integration paradigm, so-called 2.5-D integration, to handle many difficulties which are challenging to unravel utilizing conventional non-monolithic integration schemes. The ebook additionally introduces significant 3-D VLSI layout concerns that have to be solved by way of IC designers and digital layout Automation (EDA) builders. via treating 3-D integration in an built-in framework, the e-book presents very important insights for semiconductor procedure engineers, IC designers, and people operating in EDA R&D.

Dr. Yangdong Deng is an affiliate professor on the Institute of Microelectronics, Tsinghua college, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor on the division of electric and desktop Engineering, Carnegie Mellon college, USA.

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80%, can be achieved in relatively short testing time. However, a higher fault coverage level requires significantly increased testing time. 9% fault coverage and 10% of total time is enough for 80% fault coverage. 12 for Ct [31]. 16) The drawing in Fig. 2 shows the trend of silicon areas when the input VLSI application is partitioned into four layers and implemented as 4 separate dies. Clearly, fabrication cost decrease very rapidly with the increasing of fault coverage level achieved by the system components.

Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system. IEEE Trans. On Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 19, Nov. 1996, pp. 719  727. [27] S. A. Kuhn, M. B. Kleiner, P. Ramm, W. Weber. Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology. IEEE Trans. On Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 19 No.

Subramanian, M. Toita, N. R. Ibrahim, S. J. Souri, K. C. Saraswat. Low-leakage Germanium-seeded laterally-crystallized single-grain 100 nm TFTs for vertical integration applications. , Vol. 20, Jul. 1999, pp. 341  343. [11] G. W. Neudeck, S. Pae, J. P. Denton, T. Su. Multiple layers of silicon-on-insulator for nanostructure devices. J. Vac. Sci. Technol. B, Vol. 17, no. 3, 1999, pp. 994  998. [12] A. Heya, A. Masuda, H. Matsumura. Low-temperature crystallization of morphous silicon using atomic hydrogen generated by catalytic reaction on heated tungsten.

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3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme by Prof. Yangdong Deng, Prof. Wojciech P. Maly (auth.)
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