Analog Circuit Design: High-speed Clock and Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit layout comprises the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and helpful layout rules within the region of analog circuit layout. each one half is gifted by way of six specialists in that box and cutting-edge info is shared and overviewed. This publication is quantity 17 during this profitable sequence of Analog Circuit layout.

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Extra info for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management

Example text

Figure 14 displays the inclusion of open loop parameter variations in the tool. 2. Figure 15 displays the resulting closed loop step response and pole/zero locations due to the above open loop parameter variations. The step response plots allow us to quickly assess that the system has no stability issues over the range of parameter variations entered. The pole/zero locations also confirm that the system remains stable as evidenced by the fact that the poles remain in the left half of the S-plane.

V. W. Schafer, “Discrete Time Signal Processing”, Prentice Hall, NJ, 1999. A. Demir, E. L. Sangiovanni-Vincentelli, and I. Vassiliou, “Behavioral Simulation Techniques for Phase/Delay-Locked Systems”, Custom Integrated Circuits Conference (CICC), pages 453-456, 1994. H. Perrott, “Techniques for High Data Rate Modulation and Low 49 Power Operation of Fractional-N Frequency Synthesizers with Noise Shaping”, PhD Thesis, MIT, 1997. be Abstract Does fractional-N synthesis offer the way out for monolithic CMOS integration of high-quality transceivers?

Ali, “An on-chip phase-compensation technique in fractional-N frequency synthesis,” in IEEE Proceedings of ISCAS, vol. 3, May 1999, pp. 363-366. T. A. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993. B. Miller and R. Conley, “A multiple modulator fractional divider,” IEEE Transactions on Instrumentation and Measurement, vol. 40, pp. 578-583, June 1991. W. Rhee, B. Song, and A.

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Analog Circuit Design: High-speed Clock and Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
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